The present invention is directed to the field of computer and information processing, and specifically to memory devices for storing and transferring data.
Conventional memory devices for storing and transferring data within an electronic circuit are well known. One example of a memory device is a FIFO (first in first out) memory device for temporarily holding (buffering) digital data to be transferred from one location to another. As implied by its name, a FIFO memory device establishes a first in first out order which permits data to be read in the order it was written. FIFO memory devices are particularly important when data is transferred from a first clock domain controlled by a first clock frequency to a second domain controlled by a second clock frequency. For example, in PCs (personal computers), it is typically the case that a number of data buses operating at different clock speeds may be found. A first data bus may be a PCI (peripheral component interconnect) bus operating at 33 megahertz while a second data bus such as an EISA (extended industry standard architecture) bus may operate at 8 megahertz within the computer system. In order to transfer information between the PCI and EISA buses, one side of a FIFO operates at the first clock domain speed while the other side operates at the second clock speed.
A further application of FIFO memory devices is the so-called display FIFOs used in graphics display systems to buffer the data for screen refreshes. The screen is typically refreshed by draining the display FIFO at a certain read rate. However, the read rate and the write rate to fill the FIFO are different. The read rate is based on the video clock rate (VCLK) (e.g., 100 Mb/s) at which the display screen requires refreshed data while the write rate (e.g. 800 Mb/s) to fill the display FIFO is based on the memory clock (XCLK) since the memory clock is used to retrieve data from memory. FIG. 1A, below, is provided to facilitate understanding of a conventional FIFO circuitry.
FIG. 1A is a block diagram of a conventional memory circuit 100 for transferring data between a first clock domain A and a second clock domain B. In FIG. 1A, circuit 100 comprises sync circuits 102, 106 for reducing noise jitters and for providing bit synchronization during the data transfer process. Inputs to sync circuit 102 are a WRITE_DATA signal for indicating the data units to be written to memory 104, a WRITE_ADDRESS for indicating the appropriate write address, a WRITE_CONTROL signal, and a clock signal A_CLK operating at the first clock frequency. Inputs to sync circuit 106 are a READ_DATA signal for indicating the data to be read from memory 104, a READ_ADDRESS signal for providing the appropriate address, a READ_CONTROL signal and a clock signal B_CLK operating at the second clock frequency.
It should be noted that sync circuits 102, 106, respectively, are within clock domain A (the write side circuitry) which is controlled by a first clock frequency, and clock domain B (the read side circuitry) operating at a second clock frequency different from the first frequency. Other components of circuit 100 include a memory data unit 104 for storing data to be transferred between clock domains A and B; comparators 108, 114 for evaluating write and read address pointers to determine the status of memory 104, that is, whether memory 104 is full or empty; and pointer sync circuits 110, 112 for translating address pointers from one clock domain to the other.
In operation, to accurately transfer data between the clock domains, the status of memory 104 is constantly being tracked to determine when the memory device is full or empty. The status from clock domain A, for example, is obtained by employing pointer sync circuit 110 to translate the WRITE ADDRESS pointer from clock domain A to clock domain B. There, the translated WRITE ADDRESS pointer is fed into comparator 114 which compares the translated write address pointer to the READ ADDRESS pointer received from clock domain B. This comparison yields an indication as to whether memory 104 is full or empty.
A similar process occurs to determine the memory status from clock domain B. The status from clock domain B is obtained from pointer synch circuitry 112 to translate the READ ADDRESS from clock domain B to A Herein lies the disadvantage of such conventional memory circuitry. The time taken to obtain a memory status from either clock domain is relatively long, typically about 8 to 9 clocks. It takes a longer time because the write or read pointers have to be translated from one clock domain to the other. As shown, FIG. 1A illustrates a timing diagram showing the time it takes to acquire a memory status (i.e., Aempty) from clock domain A using conventional memory circuit 100. In FIG. 1A, it takes about 9 clocks to determine that memory 104 is empty. Given the foregoing disadvantages, there is a need to resolve the problems relating to conventional approaches for transferring data between different clock domains, and for efficiently obtaining the status of a memory device during the data transfer process.
A first embodiment of the present invention discloses a system for transferring data between different clock domains, and for efficiently obtaining the status of a memory device during the data transfer process. The different clock domains may be a first and a second clock domain, for example. The first clock domain is controlled by one frequency while a second clock domain is controlled by a different frequency. In other words, the embodiment is capable of functioning irrespective of the clock speeds of the first and second clock domains. In order to accomplish this data transfer functionality, the system employs, among other circuitry, a FIFO memory device for buffering the data during the data transfer process. Further, the first embodiment is capable of efficiently obtaining the status of the FIFO memory device as to whether the FIFO is full or empty, during the data transfer process. Therefore, at the very least, the first embodiment teaches a system for transferring data from a first frequency domain to a second, and vice-versa, and for tracking the status of the memory device.
In an alternate embodiment, the present invention discloses a system for determining the status of a memory device during the transfer of data from a first clock domain controlled by a first frequency to a second domain controlled by a second frequency, the second frequency being different from the first frequency. The system further includes a write control signal operating at the first clock frequency for writing the data into the memory device and a first counter circuitry operating at the first clock frequency. The first counter circuitry receives the write control signal and in response thereof increments the first counter circuitry. A second counter circuitry operating at the second clock frequency and a first sync circuitry, which similarly receives the write control signal that is received by the first counter circuitry, translates the write control signal from the first clock frequency to the second clock frequency.
Thereafter, the translated write control signal increments the second counter circuitry. Other components include a read control signal operating at the second clock frequency for initiating a read operation from the memory device and a second counter circuitry operating at the second clock frequency and receiving the read control signal. In response, the write control signal decrements the second counter circuitry. A second sync circuitry that receives the read control signal, which is similarly received by the second counter circuitry, translates the read control signal from the second clock domain to the first clock domain in order to decrement the first counter circuitry. The first counter circuitry has an output for determining, within the first clock domain, whether the memory device is full or empty.
In a further embodiment, the present invention teaches a system for tracking control signal operations occurring within a memory device when data is being transferred between a first clock domain and a second clock domain. The system includes a write control signal that implements a write control operation for transferring data into the memory device, and a first up/down counter which receives the write control signal for the purpose of incrementing the first up/down counter by a first count. Other components of the system include a second up/down counter circuitry, and a first sync circuitry, which similarly receives the write control signal received by the first counter circuitry, and translates the write control signal from the first clock domain to the second clock domain. Next, the translated write control signal increments the second counter circuitry by a first count, the first and second counters indicating the number of write operations occurring within the memory device.
The present invention, in a further aspect, is a method of using write and read control signals in an electronic circuit, for determining the status of a memory device during the transfer of data between different clock domains. The method includes a number of steps, namely, receiving the write control signal operating at the first frequency, and incrementing a first up/down counter circuitry within the first clock domain. Other steps include incrementing a second up/down counter circuitry within the second clock domain in response to receiving the write control signal, receiving the read control signal operating at the second clock frequency, decrementing the second up/down counter circuitry within the second clock domain in response to receiving the read control signal, and decrementing the first up/down counter circuitry within the first clock domain in response to receiving the write control signal. It should be observed that the status of the memory device is determinable based on the number of read and write operations occurring within each up/down counter circuitry.